1. Field of the Invention
The present invention relates to a complementary metal-oxide semiconductor (CMOS) output buffer. More specifically, the present invention discloses a CMOS-logic compliant output buffer design for clock signals which limits the output amplitude without shifting the DC cross point while preserving the duty cycle.
2. Description of the Prior Art
Complementary Metal-Oxide Semiconductor (CMOS) output stages are used to drive the inputs of one of more downstream CMOS gates by changing the output from a logical 0 to a logical 1 and vice-versa. Typically, a CMOS output clock signal is used to change the output from 0 to 1 at a given frequency.
Several international standards specify requirements for CMOS logic at various levels. Examples of these standards are JEDEC standards JESD8B, JESD80, and JESD36.
The description of JEDEC requirements are essentially determined by the standard implementation of CMOS logic outputs, which in turn drive the inputs of CMOS logic gates.
However, these standards limit designers of CMOS output buffer stages. Particularly limiting are the requirements in terms of current consumption. These limits produce an undesirable minimum power consumption constraint for the CMOS output buffer circuitry in low power designs. Due to numerous factors, such as miniaturization of electronic components, there is an increasing demand for reduced power consumption as power is a critical factor in performance.
Furthermore, problems in low power CMOS output buffer design are even more critical when applied to output clock signals, because the current consumed is repeated for every clock cycle at the period of the clock. This repeated waste of consumed power quickly lowers performance.
Several approaches to resolving the output buffer current and power consumption problems have been attempted.
A first approach is to change the logic standard and abandon the CMOS logic. This technique uses an output driven by current as in current mode logic, or differential type outputs as in Low-Voltage Differential Signaling (LVDS).
This approach has the obvious drawback of no longer being compatible with CMOS logic and of not being capable of driving CMOS input gates. Therefore, this approach is not practical for CMOS logic circuitry or designs.
A second approach is to reduce the operating voltage supply in order to reduce the power consumption for a given current, under standard CMOS output buffer implementation. This technique has resulted in changes in the CMOS output buffer implementation, from 5V down to 3.3V, 2.5V, or 1.8V. This approach is sometimes referred to as Low Voltage CMOS (LVCMOS).
However, although this technique is still compliant with CMOS, it requires changes to both the output and input stages in order to be compatible with the lower voltage standard.
To date, there have been no acceptable solutions capable of reducing the current consumption without altering the CMOS standard.
Therefore, there is a need for a high speed, low power consumption CMOS output buffer that provides breakthrough performance while maintaining CMOS compatibility.
To achieve these and other advantages and in order to overcome the disadvantages of the conventional method in accordance with the purpose of the invention as embodied and broadly described herein, the present invention provides a clipped CMOS or CMOS-logic compliant output buffer design for clock signals which limits the output amplitude without shifting the DC cross point while preserving the duty cycle.
Under a given power supply voltage, for example VDD, the power consumption is linearly dependent on the current consumption. In a CMOS implementation, the current consumed is determined by the output load. In other words, the current consumed is determined by the sum of the capacitive loads connected to the output buffer.
This represents the current required to charge and discharge this capacitive load so as to bring the signal level of the output waveform to a logic 1 or voltage out high (VOH) of VDD when charging. When discharging, the signal level of the output waveform is brought to a logic 0 or voltage output low (VOL) of 0V.
Reaching the full VDD when charging and 0V when discharging, is called rail-to-rail swing. The only instance, im which the rail-to-rail swing is not achieved, is when the output signal is forced to change back to a logic 0 or 1 before charging or discharging is complete.
Such a reduced output amplitude phenomenon is generally considered an imperfection or flaw, as it results in rising and falling edges that are too slow for an adequate switching of the downstream stages. Furthermore, it often causes the duty cycle to become asymmetrical. However, the reduced amplitude will cause the total current consumption to be lower.
The present invention exploits the reduced current from the reduced amplitude, by limiting the output waveform""s VOH to a VOHmax value less than VDD and its VOL to a VOLmin value greater than 0V in a controlled manner. This reduces the signal amplitude and current consumption, while maitaining sharp rising and falling edges as well as preserving the duty cycle.
Therefore, the present invention provides a CMOS-logic compliant output buffer that limits output amplitude without shifting the DC cross point.
As a result, the present invention provides the advantages of fast switching circuitry in line with high speed clock applications. Also, the present invention implements a threshold control symmetrical to the CMOS switching midpoint in order to preserve duty cycle. Furthermore, the present invention dramatically reduces current and power consumption of the output buffer stage as well as greatly reduces the total current and power consumption of the CMOS clock circuit.
An object of the present invention is to prevent the full signal swing of a voltage based output. By not providing a rail-to-rail output signal, the present invention provides benefits such as reduced power consumption, reduced switching time, and reduced Electromagnetic Interference (EMI).
These and other objectives of the present invention will become obvious to those of ordinary skill in the art after reading the following detailed description of preferred embodiments.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.